All CMOS IC unused input pins should be grounded all unused output pins should be kept open 4027-ground pins 9,10,11,12, and 13 if you use only one flip flop 4081-ground pins 8,9,12,13 if you use only two gates LM339-ground pins 10,11 if you use only three comparators.
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$begingroup$If I'm using an IC in the 74HC or 74HCT family, and I'm not using all the input pins, I understand that I should not leave them unconnected because they will float. But what exactly should I do with them, and what are the pros and cons of the different options?
For example, if I'm using the 74HCT08, which has four AND gates, and I'm only using two of the gates, what should I do with the inputs of the other two gates?
I've seen various recommendations in various places, such as...
- connect them directly to Vcc
- connect them directly to GND
- connect them to Vcc through a pull-up resistor
- connect them to GND through a pull-down resistor
What are the pros and cons of each of these options? Which option is best for stability and low power consumption?
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$endgroup$![Cd4047 what to do with unused inputs meaning Cd4047 what to do with unused inputs meaning](/uploads/1/2/6/2/126228951/909946540.png)
4 Answers
$begingroup$There are a few considerations that have not been mentioned in other answers.
- Sometimes the unused input plays an important role in the logic of the part. An example would be a 4-input gate where only 3 inputs are actually used. In this case the logic level that you tie the unused input to must be selected properly or else the logic function of the used functions will not work.
- In some business / industrial segments it is necessary to test all functions in each part on the board even if they are not used. This is done to ensure that some nascent fault in a chip does not expose to a higher chance of catastrophic failure of the part. The addition of pull ups or pull downs on each unused pins allows automated test equipment to toggle the pins which would not be possible if they were hard tied to VDD or GND.
- There are cases where it is handy to keep unused gates available for possible future rework to tweak the design in the case of bugs found, need to invert or combine signals or other things. Pins hard tied to VDD and GND are very much harder to rework so added pull ups or pull downs provide access pads for the rework.
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$endgroup$$begingroup$The default answer for CMOS inputs is to connect them directly to either ground or power. I would let routing dictate which. If it doesn't matter, connect them to ground.
I'd probably start out with them all connected to ground in the schematic, then maybe switch some to power during routing if it makes things easier. If you have a ground plane, then ground is the net that you can connect to while causing the least additional routing congestion.
In some cases, you can tie inputs to outputs. For example, tie all three pins of a AND gate together. It can end up in either one of two stable states, but you don't care which one. The advantage of that is possibly less routing congestion, especially if the three pins are next to each other.
Of course this trick of tying inputs to outputs doesn't work with gates that invert. Then you'd either make a oscillator or end up with the inputs floating at the absolute worst voltage for power dissipation.
Added
This has all been assuming these are inputs to totally unused gates, which is what I interpreted the question to be about. The polarity of unused inputs to used gates can certainly matter, and then you may not have a choice whether the input must be tied high or low. For example, if you are using only 3 inputs of a 4-input AND or NAND gate, then the unused forth input must be tied high for the gate to work as intended. Likewise, unused inputs to used OR or NOR gates must be tied low.
It is not necessary to tie CMOS inputs high or low thru resistors. This is not because CMOS inputs have series resistors built in, because they don't. It is because no high inrush current will flow nor any harm caused by holding a CMOS input at the power or ground level, even during power-up.
Olin LathropOlin Lathrop288k3232 gold badges360360 silver badges812812 bronze badges
$endgroup$$begingroup$Connect to either Vcc or GND. It makes no difference. With no load on the outputs, the current in the internal transistors will be about the same.
Or use a pullup or pulldown - again it makes little difference, with the proviso that you'll use more parts than necessary, and if the resistor fails open, the floating inputs may cause baffling symptoms which will be all the harder to track down since there is 'obviously' no need to check out the unused gates. I speak from experience when I say that an unused gate can produce mystifying symptoms on the output from a used gate in the same package.
Pullup/pulldown techniques are largely a hangover from earlier, pre-CMOS families.
WhatRoughBeastWhatRoughBeast51.1k22 gold badges2929 silver badges7979 bronze badges
$endgroup$$begingroup$It doesn't really matter which of the options you choose, all will do what is needed in 99.99% of the cases. And in that 0.01% of the cases that this isn't true you will know and have good reason to do something different. I can't think of any examples where this would be the case though.
Using a resistor is pointless as CMOS logic inputs are very high-ohmic so there isn't going to flow any current anyway.
That leaves connecting to ground or supply as the only options, which one you choose doesn't matter, whatever is more convenient.
CMOS logic circuits only use current when they're changing states so that's why you should apply a fixed state at the inputs. Whether that's zero, one or a combination of both doesn't matter at all.
BimpelrekkieBimpelrekkie59.6k22 gold badges6262 silver badges136136 bronze badges
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